Design and Simulation of Nano Wire FET

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M. Anil Kumar, Y.N.S. Sai Kiran, U. Jagadeesh, M. Durga Prakash (2017). Design and Simulation of Nano Wire FETMechanics, Materials Science & Engineering, Vol 9. doi:10.2412/mmse.97.91.539

Authors: M. Anil Kumar, Y.N.S. Sai Kiran, U. Jagadeesh, M. Durga Prakash

ABSTRACTAs the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. To simulate these devices, accurate modelling and design based on gate-material are necessary to assess their performance limits, since cross-sections of the multi-gate NWFETs are expected to be a few nano-meters wide in their ultimate scaling. In this paper we have explored the use of SILVACO with different materials for simulating and studying the short channel behaviour of nanowire FETs.

Keywords: nanowire, FET, threshold voltage, SILVACO

DOI 10.2412/mmse.97.91.539


[1] Yi Cui, Zhaohui Zhong, Deli Wang, Wayne U. Wang and Charles M. Lieber, High Performance Silicon Nanowire Field Effect Transistors, Department of Chemistry and Chemical Biology and Division of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts 02138 Received November 1, 2002 (NAN0 LETTERS 2003 VOL 3, NO-2, 149-152.

[2] H. S. P. Wong, “Beyond the conventional transistor” Solid State Electronics, vol. 49, pp. 755-762, May 2005

[3] J. T. Park, J. P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines” IEEE Trans. Electron Devices, Vol. 49, No. 12, pp. 2222 -2229, Dec. 2002.

[4] Iwai Hiroshi, Natori Kenji, Shiraishi Kenji, Iwata Jun-ichi, Oshiyama Atsushi, Yamada Keisaku, Ohmori Kenji, Kakushima Kuniyuki & Ahmet Parhat, “ SI Nanowire FET and its modeling”, “Science China”, MAY 2011, Vol. 54, No-5:1004-1011, DOI:10, 1007/s11432-011-4220-0.

[5] Bipul C.Paul, Ryan Tu, Shinobu Fujita, Masaki Okajima, Thomas H Lee, Yoshio Nishi, “An Analytical Compact Circuit Model for Nano Wire FET”, IEEE Transactions on Electronic Devices, Vol. 54, No.7, July 2007.


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